1. Field of Invention
The present invention relates to a thin film transistor and a fabricating method thereof which improve device characteristics by forming a substance layer such as a vacuum layer or an air layer, which has a remarkable characteristic of insulation, on an active layer.
2. Discussion of Related Art
As far as a thin film transistor(hereinafter abbreviated TFT) which becomes a crucial part of a pixel array of an active matrix liquid crystal display is concerned, an amorphous silicon layer which enables to be deposited on a wide area as swell as to be produced at a low temperature for a mass production is used for an active layer.
For the present, a driver and a pixel array are required to be integrated simultaneously. There is a certain limitation of electrical mobility of amorphous silicon for a device having a fast operation speed. That's why techniques of fabricating a TFT of low temperature polycrystalline silicon of which electrical mobility is excellent are currently studied.
The methods of forming a polycrystalline silicon layer are largely divided into a high temperature process which deposits silicon of a polycrystalline state and a low temperature process which deposits amorphous silicon and then crystallizing the amorphous silicon into a polycrystalline state by annealing. In the latter method, after an amorphous silicon layer has been deposited at around 350 C., the amorphous silicon layer is crystallized by applying energy such as laser. The crystallization of silicon proceeds by growing silicon grains. One silicon grain collides into another grains nearby to terminate its growth so that grain boundaries are generated among the silicon grains.
FIGS. 1A to FIGS. 1D show cross-sectional views of fabricating a TFT according to a related art.
Referring to FIGS. 1A, after a buffer layer 10 of silicon oxide or silicon nitride has been formed on an insulated substrate 100, an amorphous silicon layer is deposited on the buffer layer 10. Then, the amorphous silicon layer is crystallized by laser energy. An active layer 12 is formed by patterning the crystallized silicon layer by photolithography.
Referring to FIG. 1B, an insulating layer and an electrically-conductive layer are deposited successively on the active layer 12. A gate electrode 15 is patterned by etching the electrically-conductive layer by photolithography. A gate insulating layer 13 is patterned by etching the insulating layer in use of the gate electrode 15 as an etch mask.
Referring to FIG. 1C, a source region 12S and a drain region 12D as impurity regions are formed by doping the exposed surface of the active layer 12 with impurities. An unexplained sign of `12C` indicates a channel region.
Referring to FIG. 1D, a protecting layer 16 is deposited over a whole surface of the substrate. Contact holes exposing portions of the source and drain regions 12S and 12D are formed by etching predetermined portions of the protecting layer 16 by photolithography. After an electrically-conductive layer has been deposited over the substrate, a source electrode 17S and a drain electrode 17D are formed by etching the electrically-conductive layer by photolithography.
As mentioned in the above description, a polycrystalline silicon layer is formed by depositing an amorphous silicon layer on an insulated substrate at low temperature and by crystallizing the amorphous silicon layer by the irradiation of a laser beam thereon.
Once the laser beam is irradiated to the amorphous silicon layer, most of the beam energy is absorbed by the amorphous silicon layer. Thus, the silicon layer is liquidized selectively or completely. Then, the liquidized silicon layer is cooled immediately. In this process, the remaining or generated silicon particles work as crystallizing nuclei. In this case, the silicon is crystallized by the growth of silicon grains. The growth of each silicon grain is terminated by the collisions of the neighbouring grains wherein the collisions generate grain boundaries.
The existence of the boundaries in a polycrystalline silicon layer results in a rugged surface of the silicon layer. Thus, an active layer of which surface is not smooth is formed. Thereby, a gate insulating layer of which surface is contacted with the active layer shows a poor interface characteristic. Such poor interface characteristic between the active layer and the gate insulating layer causes the increases of breakdown of the thin layer, a flat band shift and an S-factor so that the characteristics of a TFT may be ruined.